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Design of cost-efficient interconnect processing units: Spidergon STNoC
پدید آورنده
/ Marcello Coppola ... [et al.]
موضوع
Networks on a chip,ST Microelectronics,Microprocessors
رده
004
.
1
D457
2009
کتابخانه
Central Library and Archive Center of shahid Beheshti University
محل استقرار
استان:
Tehran
ـ شهر:
Tehran
تماس با کتابخانه :
22431916
-
021
NATIONAL BIBLIOGRAPHY NUMBER
Number
271203
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
انگلیسی
COUNTRY OF PUBLICATION OR PRODUCTlON
Country of publication
IR
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Design of cost-efficient interconnect processing units: Spidergon STNoC
General Material Designation
[book]
First Statement of Responsibility
/ Marcello Coppola ... [et al.]
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boca Raton
Name of Publisher, Distributor, etc.
: CRC Press
Date of Publication, Distribution, etc.
، 2009
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xxi, 263 p.
Other Physical Details
: ill + 1 CD-ROM
SERIES
Series Title
System-on-chip design and technologies
GENERAL NOTES
Text of Note
Includes bibliographical references (p. 235-261) and index
TOPICAL NAME USED AS SUBJECT
Entry Element
Networks on a chip
Entry Element
ST Microelectronics
Entry Element
Microprocessors
DEWEY DECIMAL CLASSIFICATION
Number
004
.
1
D457
2009
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK5105
.
546
.
D47
2009
PERSONAL NAME - ALTERNATIVE RESPONSIBILITY
Entry Element
Coppola, Marcello
Relator Code
creator
ORIGINATING SOURCE
Country
ایران
LOCATION AND CALL NUMBER
Call Number
TK5105.546 .D47 2009
Previous cataloging
BL
1
Y
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