INTERNATIONAL STANDARD BOOK NUMBER
(Number (ISBN
0824747119
NATIONAL BIBLIOGRAPHY NUMBER
Country Code
IR
Number
EN-57035
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
انگلیسی
COUNTRY OF PUBLICATION OR PRODUCTlON
Country of publication
IR
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Domain-specific processors :
General Material Designation
[Book]
Other Title Information
:systems, architectures, modeling, and simulation
First Statement of Responsibility
/ edited by Shuvra S. Bhattacharyya, Ed F. Deprettere, JooAش?rgen Teich
fa
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
New York
Name of Publisher, Distributor, etc.
: Marcel Dekker,
Date of Publication, Distribution, etc.
, c2004.
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xv, 261 p. , ill. , 24 cm.
SERIES
Series Title
(Signal processing and communications
Volume Designation
; 20)
NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.
Text of Note
Electronic
INTERNAL BIBLIOGRAPHIES/INDEXES NOTE
Text of Note
Includes bibliographical references and index.
CONTENTS NOTE
Text of Note
7. Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures / Steven Derrien, Anne-Claire Guillou, Patrice Quinton, Tanguy Risset and Charles Wagner -- 8. Goal-Driven Reconfiguration of Polymorphous Architectures / Sumit Lohani and Shuvra S. Bhattacharyya -- 9. Realizations of the Extended Linearization Model / Alexandru Turjan, Bart Kienhuis and Ed F. Deprettere -- 10. Communication Services for Networks on Chip / Andrei Radulescu and Kees Goossens -- 11. Single-Chip Multiprocessing for Consumer Electronics / Paul Stravers and Jan Hoogerbugge -- 12. Future Directions of Programmable and Reconfigurable Embedded Processors / Stephan Wong, Stamatis Vassiliadis and Sorin Cotofana.
Text of Note
1. Automatic VHDL Model Generation of Parameterized FIR Filters / E. George Walters III, John Glossner and Michael J. Schulte -- 2. An LUT-Based High Level Synthesis Framework for Reconfigurable Architectures / Loic Lagadec, Bernard Pottier and Oscar Villellas-Guillen -- 3. Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms / David Guevorkian, Petri Liuha, Aki Launiainen and Ville Lappalainen -- 4. Stride Permutation Access in Interleaved Memory Systems / Jarmo Takala and Tuomas Jarvinen -- 5. On Modeling Intra-Task Parallelism in Task-Level Parallel Embedded Systems / Andy D. Pimentel, Frank P. Terpstra, Simon Polstra and Joe E. Coffland -- 6. Energy Estimation and Optimization for Piecewise Regular Processor Arrays / Frank Hannig and Jurgen Teich --
TOPICAL NAME USED AS SUBJECT
Embedded computer systems
Multiprocessors
LIBRARY OF CONGRESS CLASSIFICATION
Class number
E-BOOK
PERSONAL NAME - SECONDARY RESPONSIBILITY
Bhattacharyya, Shuvra S., 1968-
Deprettere, Ed. F., 1944-
Teich, JooAش?rgen, 1964-
ORIGINATING SOURCE
Country
ایران
ELECTRONIC LOCATION AND ACCESS
Host name
0824747119.pdf
Access number
عادی
Compression information
عادی
Date and Hour of Consultation and Access
0824747119.pdf
Electronic Format Type
متن
old catalog
e
BL
1
a
Y
