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Generating hardware assertion checkers
پدید آورنده
موضوع
aided design. ; Integrated circuits ; Verification. ; Error analysis (Mathematics) ; -Integrated circuits ; Very large scale integration ; Computer
رده
کتابخانه
Central Library and Documents Center of Mazandaran University
محل استقرار
استان:
Mazandaran
ـ شهر:
Babolsar
تماس با کتابخانه :
62
-
35302861
-
011
NATIONAL BIBLIOGRAPHY NUMBER
Number
oldebook10256
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
eng
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Generating hardware assertion checkers
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
[New York?] :
Name of Publisher, Distributor, etc.
: Springer,
Date of Publication, Distribution, etc.
, 2008.
NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.
Text of Note
Print
TOPICAL NAME USED AS SUBJECT
aided design. ; Integrated circuits ; Verification. ; Error analysis (Mathematics) ; -Integrated circuits ; Very large scale integration ; Computer
PERSONAL NAME - PRIMARY RESPONSIBILITY
; Zilic, Zeljko. ; -Boul?, Marc, ; 1974
old catalog
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