عنوان
پدید آورنده
موضوع
رده
TK7885.7
TK7885
.
7
کتابخانه
محل استقرار
OTHER STANDARD IDENTIFIER
Standard Number
2147
TITLE AND STATEMENT OF RESPONSIBILITY
First Statement of Responsibility
Bezerra, Eduardo Augusto
author
Title Proper
Synthesizable VHDL design for FPGAs
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
1 online resource )vii, 157 pages( : illustrations
GENERAL NOTES
Text of Note
Includes bibliographical references
TOPICAL NAME USED AS SUBJECT
Entry Element
، VHDL )Computer hardware description language(
Entry Element
، Field programmable gate arrays
Entry Element
، Engineering
Entry Element
، Circuits and Systems
Entry Element
، Electronics and Microelectronics, Instrumentation
Entry Element
، Software Engineering/Programming and Operating Systems
DEWEY DECIMAL CLASSIFICATION
Number
005
.
7/1
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK7885
.
7
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
Entry Element
Eduardo Augusto Bezerra, Djones Vinicius Lettnin
AU suiciniV senojD ,nintteL author
TI
LOCATION AND CALL NUMBER
Shelving Form of Title, Author, Author/Title
لاه دیجیتانابخکت
