High performance multi-channel high-speed I/O circuits
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
New York
Name of Publisher, Distributor, etc.
Springer
Date of Publication, Distribution, etc.
2013
SERIES
Series Title
Analog circuits and signal processing series
NOTES PERTAINING TO RESPONSIBILITY
Text of Note
This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference )ISI( mitigation and improved bit error rates )BER( at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures. Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits; Includes critical background knowledge related to channel ISI equalization circuits; Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control )AGC( circuits in current I/O systems.