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Verification techniques for system-level design
پدید آورنده
Fujita, Masahiro
موضوع
، Systems on a chip-- Testing,، Integrated circuits-- Verification,، Formal methods )Computer science(
رده
TK
7895
.
E42
.
F95
2008
کتابخانه
Central Library of Sharif University of Technology
محل استقرار
استان:
Tehran
ـ شهر:
Tehran
تماس با کتابخانه :
66005817
-
021
OTHER STANDARD IDENTIFIER
Standard Number
144949
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
بهار۷۸
.Language of Text, Soundtrack etc
English
TITLE AND STATEMENT OF RESPONSIBILITY
General Material Designation
)50(
First Statement of Responsibility
Fujita, Masahiro
Title Proper by Another Author
6591-
Title Proper
Verification techniques for system-level design
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Amsterdam; Boston
Name of Publisher, Distributor, etc.
Morgan Kaufmann Publishers
Date of Publication, Distribution, etc.
2008
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
viii, 240 p.: ill.; 25 cm
SERIES
Series Title
The Morgan Kaufmann series in systems on silicon
GENERAL NOTES
Text of Note
Includes bibliographical references and index
TOPICAL NAME USED AS SUBJECT
Entry Element
، Systems on a chip-- Testing
Entry Element
، Integrated circuits-- Verification
Entry Element
، Formal methods )Computer science(
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7895
.
E42
.
F95
2008
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
Entry Element
Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad
AU peedardnI ,hsohG 1970-
AU lukuM ,dasarP
TI
SE
LOCATION AND CALL NUMBER
Shelving Form of Title, Author, Author/Title
05
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