یادداشتهای مربوط به کتابنامه ، واژه نامه و نمایه های داخل اثر
متن يادداشت
Includes index.
یادداشتهای مربوط به مندرجات
متن يادداشت
Summary: This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.
متن يادداشت
Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions Basics (sequence, property, assert).- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- expect -- assume and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800 2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options (Reference material).
موضوع (اسم عام یاعبارت اسمی عام)
موضوع مستند نشده
Engineering
موضوع مستند نشده
Circuits and Systems
موضوع مستند نشده
Electronics and Microelectronics, Instrumentation
موضوع مستند نشده
Processor Architectures
موضوع مستند نشده
Verilog (Computer hardware description language)
موضوع مستند نشده
Electronic digital computers, Design and construction