IEEE standard for SystemVerilog--unified hardware design, specification, and verification language /
نام عام مواد
[Book]
نام نخستين پديدآور
sponsor, Design Automation Standards Committee of the IEEE Computer Society and the IEEE Standards Association Corporate Advisory Group.
وضعیت ویراست
وضعيت ويراست
2nd printing: 1 Feb. 2010. Correction to the Table of Contents.
وضعیت نشر و پخش و غیره
محل نشرو پخش و غیره
New York :
نام ناشر، پخش کننده و غيره
Institute of Electrical and Electronics Engineers,
تاریخ نشرو بخش و غیره
2010.
مشخصات ظاهری
نام خاص و کميت اثر
1 online resource (xxxvi, 1247 pages) :
ساير جزييات
illustrations
یادداشتهای مربوط به کتابنامه ، واژه نامه و نمایه های داخل اثر
متن يادداشت
Includes bibliographical references (page 1247).
یادداشتهای مربوط به خلاصه یا چکیده
متن يادداشت
Abstract: This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document. Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, PLI, programming language interface, SystemVerilog, Verilog, VPI.
عنوان اصلی به زبان دیگر
عنوان اصلي به زبان ديگر
IEEE standard for System Verilog--unified hardware design, specification, and verification language