عنوان

Advanced HDL synthesis and SOC prototyping :

شابک

9789811087769

شابک

9789811087776

شابک

9811087768

شابک

9811087776

شابک اشتباه

9789811087752

شابک اشتباه

981108775X

عنوان اصلي

Advanced HDL synthesis and SOC prototyping :

نام عام مواد

[Book]

ساير اطلاعات عنواني

RTL design using Verilog /

نام نخستين پديدآور

Vaibbhav Taraate.

محل نشرو پخش و غیره

Singapore :

نام ناشر، پخش کننده و غيره

Springer,

تاریخ نشرو بخش و غیره

[2019]

نام خاص و کميت اثر

1 online resource (319 pages)

متن يادداشت

Intro; Preface; Acknowledgements; Contents; About the Author; 1 Introduction; 1.1 Moore's Prediction and the Reality; 1.2 ASIC Designs and Shrinking Process Node; 1.3 Intel Processor Evolution; 1.4 ASIC Designs; 1.4.1 Types of ASIC; 1.5 ASIC Design Flow; 1.6 ASIC/SOC Design Challenges and Areas; 1.7 Important Takeaways and Further Discussions; References; 2 SOC Design; 2.1 SOC Designs; 2.2 SOC Design Flow; 2.2.1 Design Specifications and System Architecture; 2.2.2 RTL Design and Functional Verification; 2.2.3 Synthesis and Timing Verification; 2.2.4 Physical Design and Verification

متن يادداشت

2.2.5 Prototype and Test2.3 SOC Prototyping and Challenges; 2.4 Important Takeaways and Further Discussions; 3 RTL Design Guidelines; 3.1 RTL Design Guidelines; 3.2 RTL Design Practical Scenarios; 3.2.1 Parallel Versus Priority Logic; 3.2.2 Synopsys full_case Directive; 3.2.3 Synopsys parallel_case Directive; 3.2.4 Use of casex; 3.2.5 Use of casez; 3.3 Grouping the Terms; 3.4 Tri-State Buses and Logic; 3.5 Incomplete Sensitivity List; 3.6 Sharing of Common Resources; 3.7 Design for Multiple Clock Domain; 3.8 Ordering Temporary Variables; 3.9 Gated Clocks; 3.10 Clock Enables

متن يادداشت

3.11 Important Takeaways and Further Discussions4 RTL Design and Verification; 4.1 RTL Design Strategy for SOC; 4.2 RTL Verification Strategy for SOC; 4.3 Few Design Scenarios; 4.3.1 Shifting of the Data; 4.3.2 Synchronous Rising and Falling Edge Detection; 4.3.3 Priority Checking; 4.4 State Machines and Optimization; 4.4.1 Moore Machine; 4.4.2 Mealy Machine; 4.4.3 Moore Versus Mealy Machine; 4.5 RTL Design for Complex Designs; 4.6 RTL Design at Top Level; 4.7 Important Takeaways and Further Discussion; 5 Processor Cores and Architecture Design

متن يادداشت

5.1 Processor Architectures and Basic Parameters5.1.1 Processor and Processor Core; 5.1.2 IO Bandwidth and Clock Rate; 5.1.3 Multitasking and Processor Clock Rate; 5.2 Processor Functionality and the Architecture Design; 5.3 Processor Architecture and Micro-architecture; 5.3.1 Processor Micro-architecture; 5.4 RTL Design and Synthesis Strategies; 5.4.1 Block-Level Design; 5.4.2 Top-Level Design; 5.5 Design Scenarios; 5.5.1 Scenario 1: Instruction Set and ALU Design; 5.5.2 Scenario 2: Data Load and Shifting; 5.5.3 Scenario 3: Parallel Data Load; 5.5.4 Scenario 4: Serial Data Processing

متن يادداشت

5.5.5 Scenario 5: Program Counter5.5.6 Scenario 6: Register Files; 5.6 Performance Improvement; 5.6.1 How to Tweak the RTL to Improve the Design Performance; 5.7 Use of Processors in SOC Prototyping; 5.8 Important Takeaways and the Further Discussions; 6 Buses and Protocols in SOC Designs; 6.1 Data Transfer Schemes; 6.2 Tri-State Bus; 6.3 Serial Bus Protocols; 6.4 Bus Arbitration; 6.5 Design Scenarios; 6.5.1 Scenario 1: Static Arbitration; 6.5.2 Scenario 2: Bidirectional Data Transfer and Registered IOs; 6.5.3 Scenario 3: UART Transmitter and Receiver Design

بدون عنوان

0

بدون عنوان

8

بدون عنوان

8

بدون عنوان

8

بدون عنوان

8

متن يادداشت

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.

منبع سفارش / آدرس اشتراک

Springer Nature

شماره انبار

com.springer.onix.9789811087769

عنوان

Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog.

شماره استاندارد بين المللي کتاب و موسيقي

9789811087752

عنوان اصلي به زبان ديگر

Advanced hardware description language synthesis and system on chip prototyping :

ساير اطلاعات عنواني

real transfer level design using Verilog

موضوع مستند نشده

Systems on a chip.

موضوع مستند نشده

Verilog (Computer hardware description language)

موضوع مستند نشده

Systems on a chip.

موضوع مستند نشده

Verilog (Computer hardware description language)

موضوع مستند نشده

TEC008010

موضوع مستند نشده

TJFC

موضوع مستند نشده

TJFC

شماره

ويراست

شماره رده

نشانه اثر

مستند نام اشخاص تاييد نشده

Taraate, Vaibbhav

تاريخ عمليات

20200823223001.0

قواعد فهرست نويسي ( بخش توصيفي )

pn

نام الکترونيکي

نوع ماده

[Book]

تكميل شده

Y