edited by Anne Mignotte, Eugenio Villar, Lynn Horobin.
وضعیت نشر و پخش و غیره
محل نشرو پخش و غیره
Boston, MA
نام ناشر، پخش کننده و غيره
Springer US
تاریخ نشرو بخش و غیره
2002
مشخصات ظاهری
نام خاص و کميت اثر
(ix, 283 pages)
یادداشتهای مربوط به مندرجات
متن يادداشت
HDL Standardization --;1. VHDL-2001: What's new --;2. Verilog-2001 Behavioral and Synthesis Enhancements --;3. Advanced ASIC Sign-off Features of IEEE 1076.4-2000 and Standards Updates to Verilog and SDF --;Analog System Modeling and Design --;4. VHDL-AMS model of a synchronous oscillator including phase noise --;5. AnalogSL: A C++ Library for Modeling analog power drivers --;6. Modeling micro-mechanical structures for system simulations --;7. A Comparison of Mixed-Signal Modeling Approaches --;8. A unified IP Design Platform for extremely flexible High Performance RF and AMS Macros using Standard Design Tools --;9. Analogue Filter Synthesis from VHDL-AMS --;System Design Experiences --;10. Using GNU Make to Automate the Recompile of VHDL SoC Designs --;11. Wild Blue Yonder: Experiences in Designing an FPGA with State Machines for a Modern Fighter Jet, Using VHDL and DesignBook --;12. Analysis of Modeling and Simulation Capabilities in SystemC and Ocapi using a Video Filter Design --;13. The Guidelines and JPEG Encoder Study Case of System-Level Architecture Exploration Using the SpecC Methodology --;14. Provision and Integration of EDA Web-Services using WSDL-based Markup --;System Verification --;15. A Mixed C/Verilog Dual-Platform Simulator --;16. Assertions Targeting a Diverse Set of Verification Tools --;17. Predicting the Performance of SoC Verification Technologies --;System Specification --;18. Aspects of object-oriented hardware modeling with SystemC-Plus --;19. UML for system-level design --;20. Open PROMOL: An Experimental Language for Target Program Modification --;21. A system benchmark specification experiment with Esterel/C --;Real-Time Modeling --;22. Modeling of real-time embedded systems by using SDL --;23. A framework for specification and verification of timing constraints --;24. A general approach to modeling system-level timing constraints.
یادداشتهای مربوط به خلاصه یا چکیده
متن يادداشت
Extended Papers: Best of FDL'01 and HDLCon'01
عنوان اصلی به زبان دیگر
عنوان اصلي به زبان ديگر
Extended Papers: Best of FDL'01 and HDLCon'01
موضوع (اسم عام یاعبارت اسمی عام)
موضوع مستند نشده
Computer hardware.
موضوع مستند نشده
Computer science.
موضوع مستند نشده
Electronic data processing.
رده بندی کنگره
شماره رده
TK7885
.
7
نشانه اثر
E358
2002
نام شخص به منزله سر شناسه - (مسئولیت معنوی درجه اول )
مستند نام اشخاص تاييد نشده
edited by Anne Mignotte, Eugenio Villar, Lynn Horobin.