عنوان
پدید آورنده
موضوع
رده
TK 7888.4 .B43D4
TK
7888
.
4
.
B43D4
کتابخانه
محل استقرار
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
A designer's guide to asynchronous VLSI
First Statement of Responsibility
Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Cambridge
Name of Publisher, Distributor, etc.
Cambridge Univ. Press
Date of Publication, Distribution, etc.
c2010
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xii, 339 p.: ill.
GENERAL NOTES
Text of Note
Includes bibliographies
Text of Note
ISBN: 9780521872447
ORIGINAL VERSION NOTE
Text of Note
1
TOPICAL NAME USED AS SUBJECT
Entry Element
Computer-aided design ، Integrated circuits -- Very large scale integration
Entry Element
Design and construction ، Integrated circuits -- Very large scale integration
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7888
.
4
.
B43D4
PERSONAL NAME - PRIMARY RESPONSIBILITY
Entry Element
Beerel, Peter A.
Relator Code
AU
AU Ozdag, Recep O.
AU Ferretti, Marcos
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