عنوان

Integrated Circuits and Systems for Millimeter-Wave Frequencies

شماره

TL3sx3g52g

زبان متن نوشتاري يا گفتاري و مانند آن

انگلیسی

عنوان اصلي

Integrated Circuits and Systems for Millimeter-Wave Frequencies

نام عام مواد

[Thesis]

نام نخستين پديدآور

Mohammadnezhad, Seyed Mohammad Hossein

نام ساير پديدآوران

Heydari, Payam

نام ناشر، پخش کننده و غيره

UC Irvine

تاریخ نشرو بخش و غیره

2019

کسي که مدرک را اعطا کرده

UC Irvine

امتياز متن

2019

متن يادداشت

In the first section of this thesis, mm-wave circuit- and system-level solutions for addition of multi-user service to conventional multi-antenna phased array architectures will be introduced. The proposed architecture will enhance the link capacity, co-channel user service and hardware cost compared to conventional solutions. Theory and design of the circuits and system are detailed and comprehensive measurement results are presented verifying the system-level functionality. First section is named A Millimeter-Wave Partially-Overlapped Beamforming-MIMO Receiver: Theory, Design, and Implementation. More specifically, this section presents an analysis and design of a partially-overlapped beamforming-MIMO architecture capable of achieving higher beamforming and spatial multiplexing gains with lower number of elements compared to conventional architectures. As a proof of concept, a 4-element beamforming-MIMO receiver (RX) covering 64-67 GHz frequency band enabling 2-stream concurrent reception is designed and measured. By partitioning the RX elements into two clusters and partially overlapping these clusters to create two 3-element beamformers, both phased-array (coherent beamforming) as well as MIMO (spatial multiplexing) features are simultaneously acquired. 6-bit phase shifters with 360° phase control and 5-bit VGAs with 11 dB range are designed to enable steering of the two RX clusters toward two arbitrary angular locations corresponding to two users. Fabricated in a 130-nm SiGe BiCMOS process, the RX achieves a 30.15 dB maximum direct conversion gain and a 9.8 dB minimum noise figure (NF) across 548 MHz IF bandwidth. S-parameter-based array factor measurements verify spatial filtering of the interference and spatial multiplexing in this RX chip.In the second section of this thesis, energy-efficient ultra-high speed transceiver architectures will be presented. Current high-speed transceivers rely on high-sampling-rate high-resolution power-hungry analog-to-digital converters or digital-to-analog converters at the interface of analog and digital circuitries. However, design of these backend data-converters are extremely power-hungry at very high speeds in a fully-integrated end-to-end scenario (i.e. RF-to-Bits, Bits-to-RF). Novel system-level architectures will be presented that obviate the need for such costly data converters and will significantly relax the complexity of digital signal-processing. The proposed architecture will result in orders of magnitude energy saving at ultra-high speeds. Theory, design, and measurement results of the highest-speed, highly energy-efficient fully-integrated end-to-end transceiver will be discussed in this section. Second section is named A Millimeter-Wave Energy-Efficient Direct-Demodulation Receiver: Theory, Design, and Implementation. More precisely, this section presents the theory, design, and implementation of an 8PSK direct-demodulation receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits receiver architecture is demodulated bits, obviating the need for power-hungry high-speed-resolution data converters. A single-channel 115-135-GHz receiver prototype was fabricated in a 55-nm SiGe BiCMOS process. A max conversion gain of 32 dB and a min noise figure (NF) of 10.3 dB was measured. A data-rate of 36 Gbps was wirelessly measured at 30 cm distance with the received 8PSK signal being directly demodulated on-chip at a bit-error-rate (BER) of 1e-6. The measured receiver sensitivity at this BER is -41.28 dBm. The prototype occupies 2.5 by 3.5 mm squared of die area including PADs and test circuits (2.5 mm squared active area) and consumes a total DC power of 200.25 mW.

مستند نام اشخاص تاييد نشده

Mohammadnezhad, Seyed Mohammad Hossein

مستند نام اشخاص تاييد نشده

Heydari, Payam

مستند نام تنالگان تاييد نشده

UC Irvine

نام الکترونيکي

فرمت انتشار

p

نوع ماده

[Thesis]

کد کاربرگه

276903

سطح دسترسي

a

تكميل شده

Y