عنوان

Parasitic substrate coupling in high voltage integrated circuits :

شابک

3319743821

شابک

9783319743820

شابک اشتباه

3319743813

شابک اشتباه

9783319743813

عنوان اصلي

Parasitic substrate coupling in high voltage integrated circuits :

نام عام مواد

[Book]

ساير اطلاعات عنواني

minority and majority carriers propagation in semiconductor substrate /

نام نخستين پديدآور

Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese.

محل نشرو پخش و غیره

Cham :

نام ناشر، پخش کننده و غيره

Springer,

تاریخ نشرو بخش و غیره

2018.

نام خاص و کميت اثر

1 online resource (xvii, 183 pages) :

ساير جزييات

illustrations

عنوان فروست

Analog Circuits and Signal Processing,

شاپا ي ISSN فروست

1872-082X

متن يادداشت

Includes bibliographical references and index.

متن يادداشت

Chapter1: Overview of Parasitic Substrate Coupling -- Chapter2: Design Challenges in High Voltage ICs -- Chapter3: Substrate Modeling with Parasitic Transistors -- Chapter4: TCAD Validation of the Model -- Chapter5: Extraction Tool for the Substrate Network -- Chapter6: Parasitic Bipolar Transistors in Benchmark Structures -- Chapter7: Substrate Coupling Analysis and Evaluation of Protection Strategies.

بدون عنوان

0

متن يادداشت

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools. The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits. The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis. Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits; Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate; Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices; Offers design guidelines to reduce couplings by adding specific test protections.

منبع سفارش / آدرس اشتراک

Springer Nature

شماره انبار

com.springer.onix.9783319743820

شماره استاندارد بين المللي کتاب و موسيقي

9783319743813

موضوع مستند نشده

Integrated circuits.

موضوع مستند نشده

Interconnects (Integrated circuit technology)

موضوع مستند نشده

Circuits & components.

موضوع مستند نشده

Electronic circuits.

موضوع مستند نشده

Electronics engineering.

موضوع مستند نشده

Electronics.

موضوع مستند نشده

Engineering.

موضوع مستند نشده

Microelectronics.

موضوع مستند نشده

TECHNOLOGY & ENGINEERING-- Mechanical.

موضوع مستند نشده

TEC-- 009070

موضوع مستند نشده

TJFC

شماره

ويراست

شماره رده

نشانه اثر

مستند نام اشخاص تاييد نشده

Buccella, Pietro

مستند نام اشخاص تاييد نشده

Kayal, Maher

مستند نام اشخاص تاييد نشده

Sallese, Jean-Michel

مستند نام اشخاص تاييد نشده

Stefanucci, Camillo

تاريخ عمليات

20200823104910.0

قواعد فهرست نويسي ( بخش توصيفي )

pn

نام الکترونيکي

نوع ماده

[Book]

تكميل شده

Y