عنوان

Formal Semantics and Proof Techniques for Optimizing VHDL Models

شابک

9781461373315

شابک

9781461551232

شماره

b403337

عنوان اصلي

Formal Semantics and Proof Techniques for Optimizing VHDL Models

نام عام مواد

[Book]

نام نخستين پديدآور

by Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey.

محل نشرو پخش و غیره

Boston, MA :

نام ناشر، پخش کننده و غيره

Imprint: Springer,

تاریخ نشرو بخش و غیره

1999.

متن يادداشت

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

شماره استاندارد بين المللي کتاب و موسيقي

9781461373315

عنوان

Springer eBooks

موضوع مستند نشده

Computer engineering.

موضوع مستند نشده

Computer hardware.

موضوع مستند نشده

Computer-aided design.

موضوع مستند نشده

Engineering.

موضوع مستند نشده

Systems engineering.

مستند نام اشخاص تاييد نشده

Umamageswaran, Kothanda.

مستند نام اشخاص تاييد نشده

Pandey, Sheetanshu L.

مستند نام اشخاص تاييد نشده

Wilsey, Philip A.

مستند نام تنالگان تاييد نشده

SpringerLink (Online service)

تاريخ عمليات

20190301082100.0

نام الکترونيکي

نوع ماده

[Book]

تكميل شده

Y