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عنوان
Verification by error modeling

پدید آورنده
/ written by Katarzyna Radecka, Zeljko Zilic

موضوع
Integrated circuits -- Very large scale integration -- Computer-aided design,Integrated circuits -- Verification

رده
TK
7874
.
75
.
R33
2003

کتابخانه
Library of Campus2 Colleges of Engineering of Tehran University

محل استقرار
استان: Tehran ـ شهر: Tehran

Library of Campus2 Colleges of Engineering of Tehran University

تماس با کتابخانه : 88225387-021

INTERNATIONAL STANDARD BOOK NUMBER

(Number (ISBN
1402076525

NATIONAL BIBLIOGRAPHY NUMBER

Country Code
IR
Number
45606

LANGUAGE OF THE ITEM

.Language of Text, Soundtrack etc
انگلیسی

COUNTRY OF PUBLICATION OR PRODUCTlON

Country of publication
IR

TITLE AND STATEMENT OF RESPONSIBILITY

Title Proper
Verification by error modeling
General Material Designation
[Book]
Other Title Information
:using testing techniques in hardware verification
First Statement of Responsibility
/ written by Katarzyna Radecka, Zeljko Zilic

.PUBLICATION, DISTRIBUTION, ETC

Place of Publication, Distribution, etc.
Boston
Name of Publisher, Distributor, etc.
: Kluwer Academic Publishers
Date of Publication, Distribution, etc.
, 2003

PHYSICAL DESCRIPTION

Specific Material Designation and Extent of Item
xiv, 216 p.
Other Physical Details
: ill.
Dimensions
; 25 cm

SERIES

Series Title
Frontiers in electronic testing

GENERAL NOTES

Text of Note
English

INTERNAL BIBLIOGRAPHIES/INDEXES NOTE

Text of Note
Includes bibliographical references and index

TOPICAL NAME USED AS SUBJECT

Integrated circuits -- Very large scale integration -- Computer-aided design
Integrated circuits -- Verification

LIBRARY OF CONGRESS CLASSIFICATION

Class number
TK
7874
.
75
Book number
.
R33
2003

PERSONAL NAME - PRIMARY RESPONSIBILITY

Radecka, Katarzyna, author

PERSONAL NAME - SECONDARY RESPONSIBILITY

Zilic, Zeljko, author

ORIGINATING SOURCE

Country
Iran
Agency
University of Tehran. Library of Technical Camp 2

Old cataloging

p

BL
1

Y

Proposal/Bug Report

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