عنوان
پدید آورنده
موضوع
رده
TK 7888.4 .B7F81
TK
7888
.
4
.
B7F81
کتابخانه
محل استقرار
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Fundamentals of digital logic with verilog designs
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Tehran: Nass; Boston
Name of Publisher, Distributor, etc.
McGraw Hill
Date of Publication, Distribution, etc.
1383=2004
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xx,844 p. : illus, tables.
GENERAL NOTES
Text of Note
Includes 1 CD ROM
Text of Note
Includes bibliographical references and index
NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY
Text of Note
Stephen Brown and Zvonko Vranesic
ORIGINAL VERSION NOTE
Text of Note
1
TOPICAL NAME USED AS SUBJECT
Entry Element
، Logic circuits- Design and construction -- Data processing
Entry Element
، Logic Design- Data proccesing
Entry Element
، VHDL ) computer hardware description language(
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7888
.
4
.
B7F81
PERSONAL NAME - PRIMARY RESPONSIBILITY
Entry Element
Brown, Stephen
Relator Code
AU
AU Vranesic, Zvonko
TI
