Protecting chips against hold time violations due to variability
General Material Designation
[Book]
First Statement of Responsibility
/ Gustavo Neuberger, Gilson Wirth, Ricardo Reis
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
New York
Name of Publisher, Distributor, etc.
: Springer,
Date of Publication, Distribution, etc.
, 2013?.
NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.
Text of Note
Electronic
INTERNAL BIBLIOGRAPHIES/INDEXES NOTE
Text of Note
Includes bibliographical references..
CONTENTS NOTE
Text of Note
Summary: This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements. The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described.
Text of Note
Introduction, Process Variations and Flip-Flops -- Process Variability -- Flip-Flops and Hold Time Violations -- Circuits Under Test -- Measurement Circuits -- Experimental Results -- Systematic and Random Variablility -- Normality Tests -- Probability of Hold Time Violations -- Protecting Circuits Against Hold Time Violations -- Padding Efficiency Of the Proposed Padding Algorithm -- Final Remarks.