INTERNATIONAL STANDARD BOOK NUMBER
(Number (ISBN
9783319023779
NATIONAL BIBLIOGRAPHY NUMBER
Country Code
IR
Number
EN-57514
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
انگلیسی
COUNTRY OF PUBLICATION OR PRODUCTlON
Country of publication
IR
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Design-for-test and test optimization techniques for TSV-based 3D stacked ICs
General Material Designation
[Book]
First Statement of Responsibility
/ Brandon Noia, Krishnendu Chakrabarty
Subsequent Statement of Responsibility
; foreword by Vishwani Agrawal
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Cham
Name of Publisher, Distributor, etc.
: Springer,
Date of Publication, Distribution, etc.
, 2014.
NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.
Text of Note
Electronic
CONTENTS NOTE
Text of Note
Summary: This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.
Text of Note
Introduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions.
TOPICAL NAME USED AS SUBJECT
Three-dimensional integrated circuits, Testing
Three-dimensional integrated circuits, Design and construction
Engineering
Circuits and Systems
Processor Architectures
Semiconductors
TECHNOLOGY & ENGINEERING / Mechanical, bisacsh
LIBRARY OF CONGRESS CLASSIFICATION
Class number
E-BOOK
PERSONAL NAME - SECONDARY RESPONSIBILITY
Noia, Brandon
Chakrabarty, Krishnendu
Agrawal, Vishwani D.,1943-
ORIGINATING SOURCE
Country
ایران
ELECTRONIC LOCATION AND ACCESS
Host name
9783319023779.pdf
Access number
عادی
Compression information
عادی
Date and Hour of Consultation and Access
9783319023779.pdf
Electronic Format Type
متن
old catalog
e
BL
1
a
Y
