INTERNATIONAL STANDARD BOOK NUMBER
(Number (ISBN
9781461473237
NATIONAL BIBLIOGRAPHY NUMBER
Country Code
IR
Number
EN-57477
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
انگلیسی
COUNTRY OF PUBLICATION OR PRODUCTlON
Country of publication
IR
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
SystemVerilog assertions and functional coverage
General Material Designation
[Book]
Other Title Information
:guide to language, methodology and applications
First Statement of Responsibility
/ Ashok B. Mehta
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
New York, NY
Name of Publisher, Distributor, etc.
: Springer,
Date of Publication, Distribution, etc.
, 2013.
NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.
Text of Note
Electronic
INTERNAL BIBLIOGRAPHIES/INDEXES NOTE
Text of Note
Includes index.
CONTENTS NOTE
Text of Note
Summary: This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.
Text of Note
Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions Basics (sequence, property, assert).- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- expect -- assume and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800 2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options (Reference material).
TOPICAL NAME USED AS SUBJECT
Engineering
Circuits and Systems
Electronics and Microelectronics, Instrumentation
Processor Architectures
Verilog (Computer hardware description language)
Electronic digital computers, Design and construction
Integrated circuits, Verification
TECHNOLOGY & ENGINEERING / Mechanical, bisacsh
LIBRARY OF CONGRESS CLASSIFICATION
Class number
E-BOOK
PERSONAL NAME - SECONDARY RESPONSIBILITY
Mehta, Ashok B
ORIGINATING SOURCE
Country
ایران
ELECTRONIC LOCATION AND ACCESS
Host name
9781461473237.pdf
Access number
عادی
Compression information
عادی
Date and Hour of Consultation and Access
9781461473237.pdf
Electronic Format Type
متن
old catalog
e
BL
1
a
Y
