voltage analog CMOS circuits-The gm/ID methodology, a sizing tool for low
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Dordrecht ;London ;New York :
Name of Publisher, Distributor, etc.
: Springer,
Date of Publication, Distribution, etc.
, 2010.
NOTES PERTAINING TO PUBLICATION, DISTRIBUTION, ETC.
Text of Note
Print
TOPICAL NAME USED AS SUBJECT
Metal oxide semiconductors, Complementary ; Design and construction. ; Low voltage integrated circuits ; Design and construction. ; Linear integrated circuits ; Design and construction. ;