عنوان
پدید آورنده
موضوع
رده
TK 7871 .99 .M44 J47
TK
7871
.
99
.
M44
J47
کتابخانه
محل استقرار
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuitsthe semi-empirical and compact model approaches
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Dordrecht; London; New York
Name of Publisher, Distributor, etc.
Springer
Date of Publication, Distribution, etc.
c2010
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xvi, 171 p. : ill
SERIES
Other Title Information
Analog circuits and signal processing
GENERAL NOTES
Text of Note
In title "gm/ID" both the m and D are subscript
Text of Note
Includes bibliographical references )p.167-168( and index
NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY
Text of Note
by Paul G.A. Jespers
TOPICAL NAME USED AS SUBJECT
Entry Element
Design and construction ، Metal oxide semiconductors, Complementary
Entry Element
Design and construction ، Low voltage integrated circuits
Entry Element
Design and construction ، Linear integrated circuits
Entry Element
، Electronic books
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7871
.
99
.
M44
J47
PERSONAL NAME - PRIMARY RESPONSIBILITY
Entry Element
Jespers, Paul G.
Relator Code
AU
TI
