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عنوان
Design of phase-locked loop (PLL) for ghost cancellation chip using CMOS technology

پدید آورنده
K. S. Islam

موضوع
Applied sciences,Electrical engineering

رده

کتابخانه
Center and Library of Islamic Studies in European Languages

محل استقرار
استان: Qom ـ شهر: Qom

Center and Library of Islamic Studies in European Languages

تماس با کتابخانه : 32910706-025

NATIONAL BIBLIOGRAPHY NUMBER

Number
TLpq304415004

LANGUAGE OF THE ITEM

.Language of Text, Soundtrack etc
انگلیسی

TITLE AND STATEMENT OF RESPONSIBILITY

Title Proper
Design of phase-locked loop (PLL) for ghost cancellation chip using CMOS technology
General Material Designation
[Thesis]
First Statement of Responsibility
K. S. Islam
Subsequent Statement of Responsibility
J. S. Linder

.PUBLICATION, DISTRIBUTION, ETC

Name of Publisher, Distributor, etc.
Texas A&M University - Kingsville
Date of Publication, Distribution, etc.
1997

PHYSICAL DESCRIPTION

Specific Material Designation and Extent of Item
95

DISSERTATION (THESIS) NOTE

Dissertation or thesis details and type of degree
M.S.
Body granting the degree
Texas A&M University - Kingsville
Text preceding or following the note
1997

SUMMARY OR ABSTRACT

Text of Note
The main objective of this thesis is to design a fully integrated charge pump PLL for application and integration on a high-frequency ghost cancellation chip. Since microprocessor operate at very high clock frequency, it becomes necessary to eliminate the delay between external and internal clocks (clock skew). This thesis will deal with the design of a charge pump phase-locked loop as a part of a high-performance ghost cancellation chip set. A charge-pump phase-locked loop (CPPLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between an off-chip reference clock and the internal clock signals. This CPPLL will be fully integrated onto a ghost cancellation chip in 2.0-um CMOS technology without the need for external components. (1,2) ftnThis thesis has been partially supported by the NASA grants NAG-5-929 and NAG-9-333.

TOPICAL NAME USED AS SUBJECT

Applied sciences
Electrical engineering

PERSONAL NAME - PRIMARY RESPONSIBILITY

J. S. Linder
K. S. Islam

ELECTRONIC LOCATION AND ACCESS

Electronic name
 مطالعه متن کتاب 

p

[Thesis]
276903

a
Y

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