عنوان

A parallel binary structured LMS algorithm for transversal adaptive filters

Number

TLpq304115018

.Language of Text, Soundtrack etc

انگلیسی

Title Proper

A parallel binary structured LMS algorithm for transversal adaptive filters

General Material Designation

[Thesis]

First Statement of Responsibility

M. Eshghi

Subsequent Statement of Responsibility

J. DeGroat

Name of Publisher, Distributor, etc.

The Ohio State University

Date of Publication, Distribution, etc.

1994

Specific Material Designation and Extent of Item

159

Dissertation or thesis details and type of degree

Ph.D.

Body granting the degree

The Ohio State University

Text preceding or following the note

1994

Text of Note

The adaptation process in digital filters requires extensive calculation. This computation makes adaptation a slow and time consuming process. Simple, but versatile, parallel algorithms for adaptive filters, suitable for VLSI implementation, are in demand. In this dissertation a regular and modular parallel algorithm for an adaptive filter is presented. This parallel structure is based on the Gradient Vector Estimation Algorithm, which minimizes the Mean Square Error. In the parallel method, the tap weights of the adaptive filter are updated every s steps, whereas in the recursive algorithms, the tap weights are updated at each step. For s step update, bit strings of length s are used to derive the terms with which the tap weights of the adaptive filter are calculated. The presented parallel algorithm computes the tap weights at time n + s as a function of the tap weights at time n, the inputs from time n + 1 to n + s 1, and the desired output from time n + 1 to n + s 1. The algorithm can be mapped to a VLSI architecture that is both regular and modular and allows either expansion of the order of the filter or the degree of parallelism obtainable. A comparison between the performance of the parallel LMS algorithm, Fast Exact LMS algorithm, and the parallel binary structured LMS algorithm is presented. Based on the proposed algorithm and employing the maximum pipelining, a VHDL model for an adaptive filter is developed. This model verifies the functional behavior of the algorithm as implemented in hardware. The model also simulates the timing of the circuit. This simulation shows the highly regular and modular structure of the algorithm. It is also a practical evidence that the proposed algorithm is suitable for a VLSI implementaton.

Applied sciences

Electrical engineering

J. DeGroat

M. Eshghi

Electronic name

p

[Thesis]

276903

a

Y