Wafer-level testing and test during burn-in for integrated circuits /
General Material Designation
[Book]
First Statement of Responsibility
Sudarshan Bahukudumbi, Krishnendu Chakrabarty.
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boston :
Name of Publisher, Distributor, etc.
Artech House,
Date of Publication, Distribution, etc.
2010.
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
1 online resource (xv, 198 pages) :
Other Physical Details
illustrations
SERIES
Series Title
Artech House integrated microsystems series
INTERNAL BIBLIOGRAPHIES/INDEXES NOTE
Text of Note
Includes bibliographical references and index.
CONTENTS NOTE
Text of Note
Wafer-Level Test and Burn-In: Industry Practices and Trends -- Resource-Constrained Testing of Core-Based ScCs -- Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs -- Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation.
0
SUMMARY OR ABSTRACT
Text of Note
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.
OTHER EDITION IN ANOTHER MEDIUM
Title
Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty.