عنوان

FPGA-BASED hardware accelerators /

(Number (ISBN

303020720X

(Number (ISBN

3030207218

(Number (ISBN

3030207226

(Number (ISBN

3030207234

(Number (ISBN

9783030207205

(Number (ISBN

9783030207212

(Number (ISBN

9783030207229

(Number (ISBN

9783030207236

Erroneous ISBN

9783030207205

Title Proper

FPGA-BASED hardware accelerators /

General Material Designation

[Book]

First Statement of Responsibility

Iouliia Skliarova, Valery Sklyarov.

Place of Publication, Distribution, etc.

Cham, Switzerland :

Name of Publisher, Distributor, etc.

Springer,

Date of Publication, Distribution, etc.

[2019]

Date of Publication, Distribution, etc.

©2019

Specific Material Designation and Extent of Item

1 online resource :

Other Physical Details

illustrations

Series Title

Lecture notes in electrical engineering ;

Volume Designation

566

Text of Note

Includes bibliographical references and index.

Text of Note

Reconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design.

0

Text of Note

This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.

Source for Acquisition/Subscription Address

Springer Nature

Stock Number

com.springer.onix.9783030207212

International Standard Book Number

9783030207205

International Standard Book Number

9783030207229

International Standard Book Number

9783030207236

Field programmable gate arrays.

Field programmable gate arrays.

TECHNOLOGY & ENGINEERING-- Electronics-- Circuits-- General.

TEC-- 008010

TJFC

TJFC

Number

Edition

Class number

Skliarova, Iouliia

Sklyarov, Valery

Date of Transaction

20200823091632.0

Cataloguing Rules (Descriptive Conventions))

pn

Electronic name

[Book]

Y