عنوان
پدید آورنده
موضوع
رده
TK7885.7 .S874 2017
TK7885
.
7
.
S874
2017
کتابخانه
محل استقرار
INTERNATIONAL STANDARD BOOK NUMBER
(Number (ISBN
1546776346
(Number (ISBN
9781546776345
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /
General Material Designation
[Book]
First Statement of Responsibility
Stuart Sutherland.
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Tualatin, OR :
Name of Publisher, Distributor, etc.
Sutherland HDL, Inc.,
Date of Publication, Distribution, etc.
[2017]
Date of Publication, Distribution, etc.
©2017
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xxxi, 453 pages :
Other Physical Details
illustrations ;
Dimensions
23 cm
INTERNAL BIBLIOGRAPHIES/INDEXES NOTE
Text of Note
Includes bibliographical references and index.
PARALLEL TITLE PROPER
Parallel Title
RTL modeling with System Verilog for simulation and synthesis using System Verilog for ASIC and FPGA design
TOPICAL NAME USED AS SUBJECT
Computer simulation.
Electronic digital computers-- Design and construction.
Verilog (Computer hardware description language)
Computer simulation.
Electronic digital computers-- Design and construction.
Verilog (Computer hardware description language)
DEWEY DECIMAL CLASSIFICATION
Number
621
.
392
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK7885
.
7
Book number
.
S874
2017
PERSONAL NAME - PRIMARY RESPONSIBILITY
Sutherland, Stuart,1953-
ORIGINATING SOURCE
Date of Transaction
20200823042647.0
Cataloguing Rules (Descriptive Conventions))
rda
ELECTRONIC LOCATION AND ACCESS
Electronic name
مطالعه متن کتاب [Book]
Y
