عنوان

Mitigation of Thermally Induced Soft Errors in CMOS Nanoscale Circuits

Number

TL49986

.Language of Text, Soundtrack etc

انگلیسی

Title Proper

Mitigation of Thermally Induced Soft Errors in CMOS Nanoscale Circuits

General Material Designation

[Thesis]

First Statement of Responsibility

Md. Sofikul Islam

Subsequent Statement of Responsibility

Sayil, Selahattin

Name of Publisher, Distributor, etc.

Lamar University - Beaumont

Date of Publication, Distribution, etc.

2017

Specific Material Designation and Extent of Item

122

Text of Note

Committee members: Liu, Jiangjiang; Tcheslavski, Gleb; Wang, Ruhai

Text of Note

Place of publication: United States, Ann Arbor; ISBN=978-0-438-69848-2

Dissertation or thesis details and type of degree

D.E.

Discipline of degree

Electrical Engineering

Body granting the degree

Lamar University - Beaumont

Text preceding or following the note

2017

Text of Note

As technology advances, the semiconductor industry faces signal integrity challenges. One major concern is the radiation-induced soft errors in complementary metal oxide semiconductor (CMOS) combinational logic circuits due to the continuous scale down of feature size. As supply voltages and node capacitances are reduced, circuits become much more susceptible to radiation because node critical charge decreases. This work reports that increasing circuit temperature deteriorates circuit reliability and further increases Single Event Transient (SET) effects. Increased temperature affects the driving strength of transistors by increasing driver resistance. Therefore, if thermal impact is not considered properly, standard measures such as driver sizing may fail as temperature increases, causing a new reliability issue. Moreover, using only driver sizing technique to mitigate thermal impact on SET is not proficient because there will be greater area penalty. This work first discusses the effects of temperature on SET and then proposes a mitigation method for thermally-induced SET based on parallel circuit technique including a temperature sensor. The simulation herein shows that parallel circuit technique reduces area penalty to 18.62% for P-hit and 16.23% for N-hit, and the delay can be decreased a maximum of ~8% in the critical path compared to typical driver sizing method.

Electrical engineering

Subject Term

Applied sciences;CMOS circuits;Parallel circuit technique;SET effects;Thermal effect

Polat, Kazim Gurkan

Sayil, Selahattin

Subdivision

Electrical Engineering

Lamar University - Beaumont

Call Number

2150238534; 10743575

Electronic name

p

[Thesis]

276903

a

Y