Code Optimization Techniques for Embedded Processors :
General Material Designation
[Book]
Other Title Information
Methods, Algorithms, and Tools
First Statement of Responsibility
by Rainer Leupers.
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boston, MA
Name of Publisher, Distributor, etc.
Springer US
Date of Publication, Distribution, etc.
2000
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
(viii, 216 pages)
CONTENTS NOTE
Text of Note
1. Introduction --;2. Memory Address Computation for DSPS --;3. Register Allocation for DSP Data Paths --;4. Instruction Scheduling for Clustered VLIW Processors --;5. Code Selection for Multimedia Processors --;6. Performance Optimization with Conditional Instructions --;7. Function Inlining under Code Size Constraints --;8. Frontend Issues --;The Lance System --;9. Conclusions --;Appendices --;A --;Experimental Result Tables --;B --;Example for the LANCE V2.0 IR --;References --;About the Author.
SUMMARY OR ABSTRACT
Text of Note
The building blocks of today's and future embedded systems are complex intellectual property components, or cores, many of which are programmable processors. Due to the need for efficient embedded systems, this overhead must be very low in order to make compilers useful in practice.