Logic Synthesis for Asynchronous Controllers and Interfaces
General Material Designation
[Book]
First Statement of Responsibility
by J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Yakovlev.
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Berlin, Heidelberg :
Name of Publisher, Distributor, etc.
Imprint: Springer,
Date of Publication, Distribution, etc.
2002.
SERIES
Series Title
Springer Series in Advanced Microelectronics,
Volume Designation
8
ISSN of Series
1437-0387 ;
CONTENTS NOTE
Text of Note
Introduction -- Design Flow -- Background -- Logic Synthesis -- State Encoding -- Logic Decomposition -- Synthesis with Relative Timing -- Design Examples -- Other Work -- Conclusions -- References -- Index.
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SUMMARY OR ABSTRACT
Text of Note
This book is devoted to logic synthesis and design techniques for asynchronous circuits. It uses the mathematical theory of Petri Nets and asynchronous automata to develop practical algorithms implemented in a public domain CAD tool. Asynchronous circuits have so far been designed mostly by hand, and are thus much less common than their synchronous counterparts, which have enjoyed a high level of design automation since the mid-1970s. Asynchronous circuits, on the other hand, can be very useful to tackle clock distribution, modularity, power dissipation and electro-magnetic interference in digital integrated circuits. This book provides the foundation needed for CAD-assisted design of such circuits, and can also be used as the basis for a graduate course on logic design.