عنوان

Energy Efficient High Performance Processors : Recent Approaches for Designing Green High Performance Computing

Standard Number

electronic

Title Proper

Energy Efficient High Performance Processors : Recent Approaches for Designing Green High Performance Computing

Place of Publication, Distribution, etc.

Singapore

Name of Publisher, Distributor, etc.

Springer

Date of Publication, Distribution, etc.

2018

Specific Material Designation and Extent of Item

XIV, 165 p. 73 illus., 68 illus

Series Title

Computer Architecture and Design Methodologies

Text of Note

by Jawad Haj-Yahya, Avi Mendelson, Yosi Ben Asher, Anupam Chattopadhyay

Text of Note

This book explores energy efficiency techniques for high-performance computing )HPC( systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures )e.g. ARM(. Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling )DVFS( for memory sub-systems

Entry Element

، Electronic circuits

Entry Element

، Engineering

Entry Element

، Microprocessors

Class number

Relator Code

AU

AU Haj-Yahya, Jawad

AU Ben Asher, Yosi

AU Chattopadhyay, Anupam

AU Mendelson, Avi