عنوان
پدید آورنده
موضوع
رده
TK 7885.7 .B5284 1998
TK
7885
.
7
.
B5284
1998
کتابخانه
محل استقرار
OTHER STANDARD IDENTIFIER
Standard Number
electronic
TITLE AND STATEMENT OF RESPONSIBILITY
First Statement of Responsibility
Bhasker, Jayaram.
Title Proper
Verilog HDL synthesis :a practical primer
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Allentown, PA
Name of Publisher, Distributor, etc.
Star Galaxy Pub.
Date of Publication, Distribution, etc.
1998
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xx, 215 p. ; 23 cm
GENERAL NOTES
Text of Note
Includes bibliographical references )p. 209( and index
NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY
Text of Note
J. Bhasker
TOPICAL NAME USED AS SUBJECT
Entry Element
، Verilog )Computer hardware description language(
Entry Element
Data processing ، Logic design
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7885
.
7
.
B5284
1998
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
TI
