عنوان
پدید آورنده
موضوع
رده
TK 7868 .D5 C3945 2008
TK
7868
.
D5
C3945
2008
کتابخانه
محل استقرار
استان: Khorasan Razavi ـ شهر: Mashhad
OTHER STANDARD IDENTIFIER
Standard Number
49525
TITLE AND STATEMENT OF RESPONSIBILITY
First Statement of Responsibility
Cavanagh, Joseph J. F.
Title Proper
Digital design and Verilog HDL fundamentals
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boca Raton
Name of Publisher, Distributor, etc.
CRC Press
Date of Publication, Distribution, etc.
c2008
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
1147 p. : ill.
GENERAL NOTES
Text of Note
Includes index
NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY
Text of Note
Joseph Cavanagh
TOPICAL NAME USED AS SUBJECT
Entry Element
Computer-aided design ، Logic circuits
Entry Element
، Verilog )Computer hardware description language(
Entry Element
، Digital electronics
DEWEY DECIMAL CLASSIFICATION
Number
621
.
39/5
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7868
.
D5
C3945
2008
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
TI
LOCATION AND CALL NUMBER
Call Number Suffix
CL
