عنوان
پدید آورنده
موضوع
رده
TK 7885.7 .P35 1996
TK
7885
.
7
.
P35
1996
کتابخانه
محل استقرار
استان: Khorasan Razavi ـ شهر: Mashhad
OTHER STANDARD IDENTIFIER
Standard Number
47901
TITLE AND STATEMENT OF RESPONSIBILITY
First Statement of Responsibility
Palnitkar, Samir.
Title Proper
Verilog HDL: a guide to digital design and synthesis
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Mountain View, Calif.
Name of Publisher, Distributor, etc.
SunSoft Press
Date of Publication, Distribution, etc.
c1996
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xxxviii, 396 p. : ill. + 1 computer laser optical disc
GENERAL NOTES
Text of Note
"A Prentice Hall title."
Text of Note
Bibliography: p. 381
Text of Note
Includes index
NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY
Text of Note
Samir Palnitkar
TOPICAL NAME USED AS SUBJECT
Entry Element
، Verilog )Computer hardware description language(
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7885
.
7
.
P35
1996
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
TI
LOCATION AND CALL NUMBER
Call Number Suffix
CL
