عنوان
پدید آورنده
موضوع
رده
TK 7868 .D5 C395 2007
TK
7868
.
D5
C395
2007
کتابخانه
محل استقرار
استان: Khorasan Razavi ـ شهر: Mashhad
OTHER STANDARD IDENTIFIER
Standard Number
47020
TITLE AND STATEMENT OF RESPONSIBILITY
First Statement of Responsibility
Cavanagh, Joseph J. F.
Title Proper
Verilog HDL: digital design and modeling
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boca Raton, FL
Name of Publisher, Distributor, etc.
CRC Press
Date of Publication, Distribution, etc.
c2007
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xviii, 900 p. : ill.
GENERAL NOTES
Text of Note
Includes index
NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY
Text of Note
Joseph Cavanagh
TOPICAL NAME USED AS SUBJECT
Entry Element
، Digital electronics
Entry Element
Computer-aided design ، Logic circuits
Entry Element
، Verilog )Computer hardware description language(
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7868
.
D5
C395
2007
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
TI
LOCATION AND CALL NUMBER
Call Number Suffix
CL
