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عنوان
Logic minimization algorithms for VLSI synthesis
پدید آورنده
by Robert K. Brayton...]et al.[
موضوع
، Logic design,Very large scale integration ، Integrated circuits,Design and construction - Data processing ، Integrated circuits,، Algorithms
رده
TK
7868
.
L6
L626
1984
کتابخانه
Central Library and Information Center of Ferdowsi University of Mashhad
محل استقرار
استان:
Khorasan Razavi
ـ شهر:
Mashhad
تماس با کتابخانه :
05138806503
OTHER STANDARD IDENTIFIER
Standard Number
14356
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Logic minimization algorithms for VLSI synthesis
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boston
Name of Publisher, Distributor, etc.
Kluwer Academic Publishers
Date of Publication, Distribution, etc.
c1984
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
ix, 193 p.: ill
SERIES
Series Title
The kluwer international series in engineering and computer science; SECS 2 VLEI, computer architecture, and digital signal processing
GENERAL NOTES
Text of Note
Bibliography: p. ]174[-190
Text of Note
Includes index
NOTES PERTAINING TO TITLE AND STATEMENT OF RESPONSIBILITY
Text of Note
by Robert K. Brayton...]et al.[
TOPICAL NAME USED AS SUBJECT
Entry Element
، Logic design
Entry Element
Very large scale integration ، Integrated circuits
Entry Element
Design and construction - Data processing ، Integrated circuits
Entry Element
، Algorithms
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7868
.
L6
L626
1984
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
TI
AU Brayton, Robert king
TI Logic minimization algorithms for V.L.S.I. synthesis
SE Kluwer international series in engineering and computer science
SE Kluwer inernational series in engineering and computer science VLSI, computer architecture, and digital signal processing
LOCATION AND CALL NUMBER
Call Number Suffix
CL
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