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عنوان
VHDL :a logic synthesis approach. ]CD[
پدید آورنده
Naylor, David.,David Naylor and Simon Jones
موضوع
، VHDL )Computer hardware description language(,Data processing ، Logic design,، Computer-aided design
رده
TK7885
.
7
.
N39
1997
کتابخانه
Library and Documentation Center of Kurdistan University
محل استقرار
استان:
Kurdistan
ـ شهر:
Sanandaj
تماس با کتابخانه :
33624006
-
087
OTHER STANDARD IDENTIFIER
Standard Number
1811
TITLE AND STATEMENT OF RESPONSIBILITY
First Statement of Responsibility
Naylor, David.
Title Proper
VHDL :a logic synthesis approach. ]CD[
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
London ; New York
Name of Publisher, Distributor, etc.
Chapman & Hall
Date of Publication, Distribution, etc.
1997
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
x, 339 p. : ill. ; 24 cm.
GENERAL NOTES
Text of Note
Includes index
NOTES PERTAINING TO EDITION AND BIBLIOGRAPHIC HISTORY
Text of Note
1st ed
TOPICAL NAME USED AS SUBJECT
Entry Element
، VHDL )Computer hardware description language(
Entry Element
Data processing ، Logic design
Entry Element
، Computer-aided design
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK7885
.
7
.
N39
1997
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
Entry Element
David Naylor and Simon Jones
AU nomiS ,senoJ
TI
LOCATION AND CALL NUMBER
Shelving Form of Title, Author, Author/Title
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