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The power of assertions in SystemVerilog
پدید آورنده
Eduard Cerny ... ]et al.[
موضوع
، Verilog )Computer hardware description language(,، Integrated circuits, Verification, Data processing
رده
TK
7874
.
58
.
P69
2010
کتابخانه
Library and Documentation Center of Kurdistan University
محل استقرار
استان:
Kurdistan
ـ شهر:
Sanandaj
تماس با کتابخانه :
33624006
-
087
OTHER STANDARD IDENTIFIER
Standard Number
1968
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
The power of assertions in SystemVerilog
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
New York ;London
Name of Publisher, Distributor, etc.
Springer
Date of Publication, Distribution, etc.
2010
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xvi, 544 p. , 24 cm.
GENERAL NOTES
Text of Note
Includes bibliographical references and index.
CONTENTS NOTE
Text of Note
Pt. 1. Opening -- pt. 2. Assertions -- pt. 3. Checkers and assertion libraries.
TOPICAL NAME USED AS SUBJECT
Entry Element
، Verilog )Computer hardware description language(
Entry Element
، Integrated circuits, Verification, Data processing
DEWEY DECIMAL CLASSIFICATION
Number
621
.
381548
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7874
.
58
.
P69
2010
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
TI
Entry Element
Eduard Cerny ... ]et al.[
AU .draudE ,ynreC
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