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عنوان
Digital system design with SystemVerilog
پدید آورنده
Zwolinski, Mark
موضوع
، Verilog )Computer hardware description language(,، Electronic digital computers-- Design and construction,، Computer simulation
رده
TK
7885
.
7
.
Z86
2010
کتابخانه
Central Library of Sharif University of Technology
محل استقرار
استان:
Tehran
ـ شهر:
Tehran
تماس با کتابخانه :
66005817
-
021
OTHER STANDARD IDENTIFIER
Standard Number
151462
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
بهار۹۸
.Language of Text, Soundtrack etc
English
TITLE AND STATEMENT OF RESPONSIBILITY
General Material Designation
)91(
First Statement of Responsibility
Zwolinski, Mark
Title Proper
Digital system design with SystemVerilog
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Upper Saddle River, NJ
Name of Publisher, Distributor, etc.
Addison-Wesley
Date of Publication, Distribution, etc.
2010
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xxix, 367 p.: ill.; 24 cm.
GENERAL NOTES
Text of Note
Includes bibliographical references and index
TOPICAL NAME USED AS SUBJECT
Entry Element
، Verilog )Computer hardware description language(
Entry Element
، Electronic digital computers-- Design and construction
Entry Element
، Computer simulation
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7885
.
7
.
Z86
2010
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
Entry Element
Mark Zwolinski
TI
LOCATION AND CALL NUMBER
Shelving Form of Title, Author, Author/Title
129
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