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عنوان
Hierarchical modeling for VLSI circuit testing
پدید آورنده
Bhattacharya, Debashis
موضوع
، Integrated circuits-- Very large scale integration-- Testing,، Integrated circuits-- Very large scale integration-- Computer simulation
رده
TK
7874
.
B484
1990
کتابخانه
Central Library of Sharif University of Technology
محل استقرار
استان:
Tehran
ـ شهر:
Tehran
تماس با کتابخانه :
66005817
-
021
OTHER STANDARD IDENTIFIER
Standard Number
117101
LANGUAGE OF THE ITEM
.Language of Text, Soundtrack etc
بهار۸۷
.Language of Text, Soundtrack etc
English
TITLE AND STATEMENT OF RESPONSIBILITY
General Material Designation
)50(
First Statement of Responsibility
Bhattacharya, Debashis
1961-
Title Proper
Hierarchical modeling for VLSI circuit testing
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boston
Name of Publisher, Distributor, etc.
Kluwer Academic Publishers
Date of Publication, Distribution, etc.
c1990
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
x, 159 p.: ill.; 24 cm
SERIES
Series Title
The Kluwer international series in engineering and computer science. VLSI, computer architecture, and digital signal processing
GENERAL NOTES
Text of Note
Includes bibliographical references
TOPICAL NAME USED AS SUBJECT
Entry Element
، Integrated circuits-- Very large scale integration-- Testing
Entry Element
، Integrated circuits-- Very large scale integration-- Computer simulation
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
7874
.
B484
1990
PERSONAL NAME - PRIMARY RESPONSIBILITY
Relator Code
AU
Entry Element
by Debashis Bhattacharya, John P. Hayes
AU (kcirtaP nhoJ).P nhoJ ,seyaH 1944-
TI
LOCATION AND CALL NUMBER
Shelving Form of Title, Author, Author/Title
05
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