عنوان
پدید آورنده
موضوع
رده
TK،7885.7،.P37،2004
TK
،
7885
.
7
،.
P37
،
2004
کتابخانه
محل استقرار
English Book
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Design through Verilog HDL
First Statement of Responsibility
T.R. Padmanabhan, B.Bala Tripura Sundari
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Piscataway,NJ، Hoboken,NJ
Name of Publisher, Distributor, etc.
IEEE Press، Wiley-Interscience
Date of Publication, Distribution, etc.
2004
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xii,455p.
INTERNAL BIBLIOGRAPHIES/INDEXES NOTE
Text of Note
Includes bibliographical references(p.449-450) and index
TOPICAL NAME USED AS SUBJECT
Entry Element
Verilog ( Computer hardware dwscription language)
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
Book number
7885
.
7
Classification Record Number
.
P37
2004
PERSONAL NAME - PRIMARY RESPONSIBILITY
Entry Element
Patmanapan, Ti. Ar
PERSONAL NAME - SECONDARY RESPONSIBILITY
Entry Element
Tripura Sundari, B.Bala
