عنوان
پدید آورنده
موضوع
رده
TK،7888.4،.L6,B7،2003
TK
،
7888
.
4
،.
L6
,
B7
،
2003
کتابخانه
محل استقرار
English Book
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Fundamentals of Digital Logic with Verilog Design
First Statement of Responsibility
Stephen Brown and Zvonko Vranesi
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Tehran
Name of Publisher, Distributor, etc.
Nas
Date of Publication, Distribution, etc.
1384 =2005
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
xx,844 P.:ill., tab.] 1 CD-ROM
TOPICAL NAME USED AS SUBJECT
Entry Element
Logic Circuits -- Design & Construction -- Data Processing
Entry Element
Logic Design -- Data Processing
Entry Element
Verilog (Computer Hardware description language)
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
Book number
7888
.
4
Classification Record Number
.
L6
,
B7
2003
PERSONAL NAME - PRIMARY RESPONSIBILITY
Entry Element
Brown, Stephen
PERSONAL NAME - SECONDARY RESPONSIBILITY
Entry Element
Vranesic, Zvonko
