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عنوان
Logic minimization algorithms for vlsi synthesis
پدید آورنده
By Robert K. Brayton ... [et al.]&
موضوع
Logic design,Integrated circuits- Very large scale integration,Integrated circuits- Design and construction- Data processing,Algorithms
رده
TK
،
7868
،.
L6
,
E78
،
1984
کتابخانه
Central Library and Information Center of Shahed University
محل استقرار
استان:
Tehran
ـ شهر:
Tehran
تماس با کتابخانه :
51214110
-
021
English Book
TITLE AND STATEMENT OF RESPONSIBILITY
Title Proper
Logic minimization algorithms for vlsi synthesis
First Statement of Responsibility
By Robert K. Brayton ... [et al.]&
.PUBLICATION, DISTRIBUTION, ETC
Place of Publication, Distribution, etc.
Boston
Name of Publisher, Distributor, etc.
Kluwer academic publishers
Date of Publication, Distribution, etc.
1984
PHYSICAL DESCRIPTION
Specific Material Designation and Extent of Item
ix, 193 p
INTERNAL BIBLIOGRAPHIES/INDEXES NOTE
Text of Note
Index
Text of Note
Bibliography
TOPICAL NAME USED AS SUBJECT
Entry Element
Logic design
Entry Element
Integrated circuits- Very large scale integration
Entry Element
Integrated circuits- Design and construction- Data processing
Entry Element
Algorithms
LIBRARY OF CONGRESS CLASSIFICATION
Class number
TK
Book number
7868
Classification Record Number
.
L6
,
E78
1984
PERSONAL NAME - SECONDARY RESPONSIBILITY
Entry Element
Brayton, Robert King
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