عنوان

Design of phase-locked loop (PLL) for ghost cancellation chip using CMOS technology

شماره

TLpq304415004

زبان متن نوشتاري يا گفتاري و مانند آن

انگلیسی

عنوان اصلي

Design of phase-locked loop (PLL) for ghost cancellation chip using CMOS technology

نام عام مواد

[Thesis]

نام نخستين پديدآور

K. S. Islam

نام ساير پديدآوران

J. S. Linder

نام ناشر، پخش کننده و غيره

Texas A&M University - Kingsville

تاریخ نشرو بخش و غیره

1997

نام خاص و کميت اثر

95

جزئيات پايان نامه و نوع درجه آن

M.S.

کسي که مدرک را اعطا کرده

Texas A&M University - Kingsville

امتياز متن

1997

متن يادداشت

The main objective of this thesis is to design a fully integrated charge pump PLL for application and integration on a high-frequency ghost cancellation chip. Since microprocessor operate at very high clock frequency, it becomes necessary to eliminate the delay between external and internal clocks (clock skew). This thesis will deal with the design of a charge pump phase-locked loop as a part of a high-performance ghost cancellation chip set. A charge-pump phase-locked loop (CPPLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between an off-chip reference clock and the internal clock signals. This CPPLL will be fully integrated onto a ghost cancellation chip in 2.0-um CMOS technology without the need for external components. (1,2) ftnThis thesis has been partially supported by the NASA grants NAG-5-929 and NAG-9-333.

موضوع مستند نشده

Applied sciences

موضوع مستند نشده

Electrical engineering

مستند نام اشخاص تاييد نشده

J. S. Linder

مستند نام اشخاص تاييد نشده

K. S. Islam

نام الکترونيکي

فرمت انتشار

p

نوع ماده

[Thesis]

کد کاربرگه

276903

سطح دسترسي

a

تكميل شده

Y