عنوان
پدید آورنده
موضوع
رده
TK,7874.75,.R33,2003
TK
,
7874
.
75
,.
R33
,
2003
کتابخانه
محل استقرار
(alk. paper)
1402076525
IR
ebook21483
انگلیسی
IR
Verification by error modeling
[Electronic Resource]
:using testing techniques in hardware verification
/ written by Katarzyna Radecka, Zeljko Zilic
Boston
: Kluwer Academic Publishers,
, 2003.
xiv, 216 p.
: ill. ; 25 cm.
(Frontiers in electronic testing
; 25)
e
Includes bibliographical references and index.
Integrated circuits--Very large scale integration--Computer-aided design
Integrated circuits--Verification
Error analysis (Mathematics)
621
.
39
,
5
TK
,
7874
.
75
,.
R33
,
2003
Radecka, Katarzyna
Zilic, Zeljko
ایران
621.39,5
1402076525.pdf
0
old catalog
e
BL
1
a
Y
