Low-power variation-tolerant design in nanometer silico
[Book]
/ Swarup Bhunia, Saibal Mukhopadhyay, editors
New York
: Springer,
, c2011.
1 online resource (xv, 440 p.)
: , ill.
Print
Includes bibliographical references and index.
Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance.
Preface; Why a New Book; Unique Features; Organization and Overview of the Content; Part I: Physics of Power Dissipations and Parameter Variations; Part II: Circuit-Level Design Solutions; Part III: System-Level Design Solutions; Part IV: Low-Power and Robust Reconfigurable Computing; Contents; Contributors; About the Editors; Part I Physics of Power Dissipations and Parameter Variations; 1 Variations: Sources and Characterization; 2 Power Dissipation; Part II Circuit-Level Design Solutions; 3 Effect of Variations and Variation Tolerance in Logic Circuits.
Low voltage integrated circuits
Low voltage integrated circuits, Design and construction