عنوان
پدید آورنده
موضوع
رده
کتابخانه
محل استقرار
oldebook31549
eng
Verification by error modeling
Boston :
: Kluwer Academic Publishers,
, 2003.
Print
aided design. ; Integrated circuits ; Verification. ; Error analysis (Mathematics) ; -Integrated circuits ; Very large scale integration ; Computer
Radecka, Katarzyna. ; Zilic, Zeljko. ;
old catalog
