عنوان
پدید آورنده
موضوع
رده
کتابخانه
محل استقرار
oldebook18652
eng
timing simulation and the degradation delay model-Logic
London :
: Imperial College Press,
, 2006.
Print
Timing circuits. ; Integrated circuits ; Very large scale integration. ; Metal oxide semiconductors, Complementary. ;
; Juan Chico, Jorge. ; Valencia, Manuel. ; -Bellido, Manuel J., ; 1964
old catalog
