Integrated system-level modeling of network-on-chip enabled multi-processor platforms /
[Book]
Tim Kogel, Rainer Leupers, Heinrich Meyr.
Dordrecht :
Springer,
2006.
1 online resource (xiv, 199 pages) :
illustrations
Includes bibliographical references and index.
Foreword. Preface -- 1. Introduction -- 2. Embedded SOC Applications -- 3. Classification of Platform Elements -- 4. System Level Design Principles -- 5. Related Work -- 6. Methodology Overview -- 7. Unified Timing Model -- 8. MP-SOC Simulation Framework -- 9. Case Study -- 10. Summary -- Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework -- List of Figures. List of Tables. References -- Index.
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"Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models."--Jacket.
Springer
978-1-4020-4825-8
Integrated system-level modeling of network-on-chip enabled multi-processor platforms.