optimization algorithms for memory architecture aware compilation /
by Lars Wehmeyer and Peter Marwedel.
Dordrecht :
Springer,
2006.
1 online resource (xi, 257 pages) :
illustrations
Includes bibliographical references and index.
Abstract; Introduction; Models and Tools; Scratchpad Memory Optimizations; Main Memory Optimizations; Register File Optimization; Summary; Future Work.
0
Presents techniques for designing fast, energy-efficient and timing predictable memory systems. This book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. It considers the impact of the register file, which is also part of the memory hierarchy.
Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002.