عنوان

RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /

1546776346

9781546776345

RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /

[Book]

Stuart Sutherland.

Tualatin, OR :

Sutherland HDL, Inc.,

[2017]

xxxi, 453 pages :

illustrations ;

23 cm

Includes bibliographical references and index.

RTL modeling with System Verilog for simulation and synthesis using System Verilog for ASIC and FPGA design

Computer simulation.

Electronic digital computers-- Design and construction.

Verilog (Computer hardware description language)

Computer simulation.

Electronic digital computers-- Design and construction.

Verilog (Computer hardware description language)

621

392

TK7885

S874

2017

Sutherland, Stuart,1953-

20200823042647.0

rda

[Book]